In a digital transmission network, data from a large number or users are serially transmitted from one network node to another, up to their respective final destination. Efficiency is achieved through combining use of high speed links between the various network nodes, and so-called Time Division Multiplex (TDM) techniques whereby the data provided by said users are multiplexed over a common frame for being fed onto a same link or trunk facility. Each user is being assigned one or several frame slots for inserting data therein. For instance, a T1 fixed length frame might include 32 slots, numbered zero to thirty one. Each slot content path throughout the network will depend upon the final considered data destination as well as upon dynamically assigned network path.
Usually, several network nodes have to be flown through between any transmitting user and the corresponding final data destination. At each node incoming frames have to be individually identified. Each slot data are deserialized and temporarily stored into a memory until time is reached for reinserting said data into a node outgoing frame slot toward the next node. Each node is provided with several ports and the data handling process has to be very fast and yet free of any error or loss of data.
Generally, the deserializing and correlative serializing operations are performed into a network interface, and then the data transfers to and from memory are micro-processor controlled. Obviously those data transfers have to be properly synchronized.
Conventionally, a synchronization or clock information is derived from a slot content within each node incoming frame. Said clock is, in turn, used to synchronize outgoing frames. In other words, data transfers between network interface adapter and memory are not fully monitored. Should a failure occur in the transfer flow, the system may not be aware of it. Consequently, for instance, same byte may be sent repetitively without any error indication being provided by the network interface.
One object of this invention is to provide a mechanism with the capability of continuously monitoring network node frame synchronization.
Another object of this invention is to provide frame data transfer synchronizing mechanism enabling monitoring data transfers in both directions within a network node as well as providing means for on-line diagnostic.
More particularly, an object of this invention is to provide a frame transfer mechanism for a processor controlled network node connected to network link, wherein fixed length data frames including a fixed number of slots are received as input frames including individual slot contents to be transferred and stored into a memory for later transmission within output frames over the network link, said frame transfer mechanism including:
a network adapter including deserializing/serializing means connected to said link for deserializing the received frame slots contents to be transferred to the memory, or serializing the memory provided data to be transmitted onto the link;
FIFO like shift register means connected between said memory and said serializing/deserializing means as FIFO-OUT and FIFO-IN means respectively, said FIFO's including an extra-bit position as compared to the defined frame slot length;
shifting means for shifting FIFO's contents;
means for inserting a flag bit into a predefined FIFO-OUT extra bit position;
means sensitive to a received frame over the link to derive a network synchronization signal therefrom;
synchronization logic means sensitive to said FIFO-OUT flag bit detection and to said network synchronization signal concurrence to derive therefrom an indication of normal synchronized transfer mechanism operation.
This and other objects, characteristics and advantages of the present invention will become more readily apparent from the following specifications when taken in conjunction with the figures.